[mirrors/Designs.git] / electronics / old / darlington_amp.sch

v 20110115 2
C 40000 40000 0 0 0 title-B.sym
C 40600 47700 1 0 0 input-1.sym
{
T 40600 48000 5 10 0 0 0 0 1
device=INPUT
}
C 40700 46100 1 0 0 input-1.sym
{
T 40700 46400 5 10 0 0 0 0 1
device=INPUT
}
C 41500 49000 1 0 0 3.3V-plus-1.sym
C 41800 45900 1 0 0 gnd-1.sym
C 41200 48200 1 0 0 pot-1.sym
{
T 42000 49100 5 10 0 0 0 0 1
device=VARIABLE_RESISTOR
T 41800 48600 5 10 1 1 0 0 1
refdes=R?
T 42000 49700 5 10 0 0 0 0 1
footprint=none
}
C 42600 46900 1 0 0 darlington_NPN-1.sym
{
T 44000 48000 5 10 0 0 0 0 1
device=darlington, NPN
T 44000 47600 5 10 0 0 0 0 1
footprint=TO92
T 43100 47070 5 10 1 1 0 0 1
refdes=T?
}
N 41400 47800 42600 47800 4
N 42600 47800 42600 48300 4
N 42600 48300 42100 48300 4
N 41700 49000 41700 48800 4
N 41700 49000 43600 49000 4
N 43600 49000 43600 48600 4
C 45100 46100 1 0 0 output-1.sym
{
T 45200 46400 5 10 0 0 0 0 1
device=OUTPUT
}
C 45100 46800 1 0 0 output-1.sym
{
T 45200 47100 5 10 0 0 0 0 1
device=OUTPUT
}
N 45100 46900 43600 46900 4
N 41500 46200 45100 46200 4
C 40700 43100 1 0 0 input-1.sym
{
T 40700 43400 5 10 0 0 0 0 1
device=INPUT
}
C 40800 41200 1 0 0 input-1.sym
{
T 40800 41500 5 10 0 0 0 0 1
device=INPUT
}
C 41600 44400 1 0 0 3.3V-plus-1.sym
C 41900 41000 1 0 0 gnd-1.sym
C 41300 43600 1 0 0 pot-1.sym
{
T 42100 44500 5 10 0 0 0 0 1
device=VARIABLE_RESISTOR
T 41900 44000 5 10 1 1 0 0 1
refdes=R?
T 42100 45100 5 10 0 0 0 0 1
footprint=none
}
C 42700 42300 1 0 0 darlington_NPN-1.sym
{
T 44100 43400 5 10 0 0 0 0 1
device=darlington, NPN
T 44100 43000 5 10 0 0 0 0 1
footprint=TO92
T 43200 42470 5 10 1 1 0 0 1
refdes=T?
}
N 41500 43200 42700 43200 4
N 42700 43200 42700 43700 4
N 42700 43700 42200 43700 4
N 41800 44400 41800 44200 4
N 41800 44400 43700 44400 4
N 43700 44400 43700 44000 4
C 45200 41200 1 0 0 output-1.sym
{
T 45300 41500 5 10 0 0 0 0 1
device=OUTPUT
}
C 45200 42200 1 0 0 output-1.sym
{
T 45300 42500 5 10 0 0 0 0 1
device=OUTPUT
}
N 41600 41300 45200 41300 4
C 43800 41500 1 0 0 pot-2.sym
{
T 44600 42400 5 10 0 0 0 0 1
device=VARIABLE_RESISTOR
T 44400 41900 5 10 1 1 0 0 1
refdes=R?
T 44600 43000 5 10 0 0 0 0 1
footprint=none
}
N 43700 42300 44300 42300 4
N 44300 42300 44300 42100 4
N 44700 41300 44700 41600 4
C 44300 42100 1 0 0 capacitor-2.sym
{
T 44500 42800 5 10 0 0 0 0 1
device=POLARIZED_CAPACITOR
T 44500 42600 5 10 1 1 0 0 1
refdes=C?
T 44500 43000 5 10 0 0 0 0 1
symversion=0.1
}
Commit	Line	Data
f13e83b5 H	1	v 20110115 2
	2	C 40000 40000 0 0 0 title-B.sym
	3	C 40600 47700 1 0 0 input-1.sym
	4	{
	5	T 40600 48000 5 10 0 0 0 0 1
	6	device=INPUT
	7	}
	8	C 40700 46100 1 0 0 input-1.sym
	9	{
	10	T 40700 46400 5 10 0 0 0 0 1
	11	device=INPUT
	12	}
	13	C 41500 49000 1 0 0 3.3V-plus-1.sym
	14	C 41800 45900 1 0 0 gnd-1.sym
	15	C 41200 48200 1 0 0 pot-1.sym
	16	{
	17	T 42000 49100 5 10 0 0 0 0 1
	18	device=VARIABLE_RESISTOR
	19	T 41800 48600 5 10 1 1 0 0 1
	20	refdes=R?
	21	T 42000 49700 5 10 0 0 0 0 1
	22	footprint=none
	23	}
	24	C 42600 46900 1 0 0 darlington_NPN-1.sym
	25	{
	26	T 44000 48000 5 10 0 0 0 0 1
	27	device=darlington, NPN
	28	T 44000 47600 5 10 0 0 0 0 1
	29	footprint=TO92
	30	T 43100 47070 5 10 1 1 0 0 1
	31	refdes=T?
	32	}
	33	N 41400 47800 42600 47800 4
	34	N 42600 47800 42600 48300 4
	35	N 42600 48300 42100 48300 4
	36	N 41700 49000 41700 48800 4
	37	N 41700 49000 43600 49000 4
	38	N 43600 49000 43600 48600 4
	39	C 45100 46100 1 0 0 output-1.sym
	40	{
	41	T 45200 46400 5 10 0 0 0 0 1
	42	device=OUTPUT
	43	}
	44	C 45100 46800 1 0 0 output-1.sym
	45	{
	46	T 45200 47100 5 10 0 0 0 0 1
	47	device=OUTPUT
	48	}
	49	N 45100 46900 43600 46900 4
	50	N 41500 46200 45100 46200 4
	51	C 40700 43100 1 0 0 input-1.sym
	52	{
	53	T 40700 43400 5 10 0 0 0 0 1
	54	device=INPUT
	55	}
	56	C 40800 41200 1 0 0 input-1.sym
	57	{
	58	T 40800 41500 5 10 0 0 0 0 1
	59	device=INPUT
	60	}
	61	C 41600 44400 1 0 0 3.3V-plus-1.sym
	62	C 41900 41000 1 0 0 gnd-1.sym
	63	C 41300 43600 1 0 0 pot-1.sym
	64	{
65	T 42100 44500 5 10 0 0 0 0 1
66	device=VARIABLE_RESISTOR
67	T 41900 44000 5 10 1 1 0 0 1
68	refdes=R?
69	T 42100 45100 5 10 0 0 0 0 1
70	footprint=none
71	}
72	C 42700 42300 1 0 0 darlington_NPN-1.sym
73	{
74	T 44100 43400 5 10 0 0 0 0 1
75	device=darlington, NPN
76	T 44100 43000 5 10 0 0 0 0 1
77	footprint=TO92
78	T 43200 42470 5 10 1 1 0 0 1
79	refdes=T?
80	}
81	N 41500 43200 42700 43200 4
82	N 42700 43200 42700 43700 4
83	N 42700 43700 42200 43700 4
84	N 41800 44400 41800 44200 4
85	N 41800 44400 43700 44400 4
86	N 43700 44400 43700 44000 4
87	C 45200 41200 1 0 0 output-1.sym
88	{
89	T 45300 41500 5 10 0 0 0 0 1
90	device=OUTPUT
91	}
92	C 45200 42200 1 0 0 output-1.sym
93	{
94	T 45300 42500 5 10 0 0 0 0 1
95	device=OUTPUT
96	}
97	N 41600 41300 45200 41300 4
98	C 43800 41500 1 0 0 pot-2.sym
99	{
100	T 44600 42400 5 10 0 0 0 0 1
101	device=VARIABLE_RESISTOR
102	T 44400 41900 5 10 1 1 0 0 1
103	refdes=R?
104	T 44600 43000 5 10 0 0 0 0 1
105	footprint=none
106	}
107	N 43700 42300 44300 42300 4
108	N 44300 42300 44300 42100 4
109	N 44700 41300 44700 41600 4
110	C 44300 42100 1 0 0 capacitor-2.sym
111	{
112	T 44500 42800 5 10 0 0 0 0 1
113	device=POLARIZED_CAPACITOR
114	T 44500 42600 5 10 1 1 0 0 1
115	refdes=C?
116	T 44500 43000 5 10 0 0 0 0 1
117	symversion=0.1
118	}