--- /dev/null
+_*
+*.cmd
+*.net
+*.backup
+*.ps
+*.eps
+*~
+*-
--- /dev/null
+v 20110115 2
+C 40000 40000 0 0 0 title-B.sym
+C 42200 47500 1 0 0 lm358-1.sym
+{
+T 42875 48100 5 10 0 0 0 0 1
+device=LM358
+T 42900 48850 5 10 0 0 0 0 1
+footprint=DIP8
+T 42400 48400 5 10 1 1 0 0 1
+refdes=(or LM386)
+}
+C 40700 47800 1 0 0 pwrjack-1.sym
+{
+T 40800 48300 5 10 0 0 0 0 1
+device=PWRJACK
+T 40700 48300 5 10 1 1 0 0 1
+refdes=AUDIO IN
+}
+C 44500 47400 1 0 0 4066-1.sym
+{
+T 44800 49950 5 10 0 0 0 0 1
+device=4066
+T 46300 49800 5 10 1 1 0 6 1
+refdes=U?
+T 44800 50150 5 10 0 0 0 0 1
+footprint=DIP14
+}
+C 42000 47200 1 0 0 ground.sym
+C 41600 47600 1 0 0 ground.sym
+N 41600 47900 41800 47900 4
+N 41600 48100 42200 48100 4
+C 48100 49600 1 180 0 pwrjack-1.sym
+{
+T 48000 49100 5 10 0 0 180 0 1
+device=PWRJACK
+T 48100 49100 5 10 1 1 180 0 1
+refdes=AUDIO OUT
+}
+N 47200 49500 46600 49500 4
+C 46700 49000 1 0 0 ground.sym
+N 46900 49300 47200 49300 4
+C 43400 47700 1 0 0 capacitor-1.sym
+{
+T 43600 48400 5 10 0 0 0 0 1
+device=CAPACITOR
+T 43600 48200 5 10 1 1 0 0 1
+refdes=C?
+T 43600 48600 5 10 0 0 0 0 1
+symversion=0.1
+}
+C 44400 47000 1 90 0 resistor-2.sym
+{
+T 44050 47400 5 10 0 0 90 0 1
+device=RESISTOR
+T 44100 47200 5 10 1 1 90 0 1
+refdes=R?
+}
+C 44100 46700 1 0 0 ground.sym
+N 44300 47900 44500 47900 4
+C 44500 49700 1 180 0 voltage-3.sym
+{
+T 44300 49000 5 8 0 0 180 0 1
+device=VOLTAGE_SOURCE
+T 44200 49200 5 10 1 1 180 0 1
+refdes=V?
+}
+C 43400 49200 1 0 0 ground.sym
+N 43200 47900 43400 47900 4
+N 42200 47500 42200 47700 4
--- /dev/null
+# Harvie's electroprojects
+Some schematics, PCB designs and other electronics related stuff
+
+http://blog.harvie.cz/
+
+### Usefull Software
+ * http://www.gpleda.org/
--- /dev/null
+# release: pcb 20100929
+# date: Mon Jun 20 04:40:22 2011
+# user: harvie ()
+# host: insomnia
+
+# To read pcb files, the pcb version (or the git source date) must be >= the file version
+FileVersion[20100606]
+
+PCB["" 275591 275591]
+
+Grid[1.000000 0 0 1]
+Cursor[0 0 0.000000]
+PolyArea[200000000.000000]
+Thermal[0.500000]
+DRC[1000 1000 1000 1000 1500 1000]
+Flags("rubberband,nameonpcb,clearnew,snappin")
+Groups("1,c:2,s:3:4:5:6:7:8")
+Styles["Signal,1000,3600,2000,1000:Power,2500,6000,3500,1000:Fat,4000,6000,3500,1000:Skinny,600,2402,1181,600"]
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+(
+ SymbolLine(0 30 20 30 8)
+ SymbolLine(0 50 20 30 8)
+ SymbolLine(0 50 20 50 8)
+)
+Symbol('{' 12)
+(
+ SymbolLine(5 15 10 10 8)
+ SymbolLine(5 15 5 25 8)
+ SymbolLine(0 30 5 25 8)
+ SymbolLine(0 30 5 35 8)
+ SymbolLine(5 35 5 45 8)
+ SymbolLine(5 45 10 50 8)
+)
+Symbol('|' 12)
+(
+ SymbolLine(0 10 0 50 8)
+)
+Symbol('}' 12)
+(
+ SymbolLine(0 10 5 15 8)
+ SymbolLine(5 15 5 25 8)
+ SymbolLine(5 25 10 30 8)
+ SymbolLine(5 35 10 30 8)
+ SymbolLine(5 35 5 45 8)
+ SymbolLine(0 50 5 45 8)
+)
+Symbol('~' 12)
+(
+ SymbolLine(0 35 5 30 8)
+ SymbolLine(5 30 10 30 8)
+ SymbolLine(10 30 15 35 8)
+ SymbolLine(15 35 20 35 8)
+ SymbolLine(20 35 25 30 8)
+)
+Attribute("HRç\b@&# " "\bð\e \1c ")
+Via[39371 98426 6000 2000 0 3500 "" ""]
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+Via[88583 118111 6000 2000 0 3500 "" ""]
+Via[88583 127953 6000 2000 0 3500 "" ""]
+Via[98425 167324 6000 2000 0 3500 "" "thermal(1X)"]
+Via[108268 167324 6000 2000 0 3500 "" ""]
+Via[88583 167324 6000 2000 0 3500 "" "thermal(1X)"]
+Via[78740 167324 6000 2000 0 3500 "" ""]
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+Via[88583 78741 6000 2000 0 3500 "" ""]
+Via[108268 68899 6000 2000 0 3500 "" "thermal(1X)"]
+Via[29528 39371 6000 2000 0 3500 "" ""]
+Via[39370 39371 6000 2000 0 3500 "" ""]
+Via[49213 39371 6000 2000 0 3500 "" ""]
+Via[108268 49214 6000 2000 0 3500 "" ""]
+Via[68898 39371 6000 2000 0 3500 "" "thermal(1X)"]
+Via[78740 39371 6000 2000 0 3500 "" ""]
+Via[88583 39371 6000 2000 0 3500 "" ""]
+Via[98425 39371 6000 2000 0 3500 "" ""]
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+Via[59055 39371 6000 2000 0 3500 "" ""]
+Via[108268 39371 6000 2000 0 3500 "" ""]
+Via[108268 59056 6000 2000 0 3500 "" "thermal(1X)"]
+Via[29528 157481 6000 2000 0 3500 "" ""]
+Via[29528 137796 6000 2000 0 3500 "" ""]
+Via[68898 167323 6000 2000 0 3500 "" ""]
+Via[19685 187008 6000 2000 0 3500 "" "thermal(0X,1X)"]
+Via[118110 187008 6000 2000 0 3500 "" "thermal(1X)"]
+Via[19685 29528 6000 2000 0 3500 "" "thermal(1X)"]
+Via[118110 29528 6000 2000 0 3500 "" "thermal(1X)"]
+Layer(1 "component")
+(
+ Polygon("clearpoly")
+ (
+ [25657 170345] [72584 170345] [72584 163931] [25657 163931]
+ )
+ Polygon("clearpoly")
+ (
+ [93987 173027] [112785 173027] [112785 162872] [93987 162872]
+ )
+ Polygon("clearpoly")
+ (
+ [73893 173460] [92259 173460] [92259 162440] [73893 162440]
+ )
+ Polygon("clearpoly")
+ (
+ [35110 124912] [37473 124912] [37473 121199] [35110 121199]
+ )
+ Polygon("clearpoly")
+ (
+ [94798 82128] [84535 82128] [84535 55120] [94798 55120]
+ )
+ Polygon("clearpoly")
+ (
+ [24037 32973] [53475 32973] [53475 43777] [24037 43777]
+ )
+ Polygon("clearpoly")
+ (
+ [74001 34864] [101820 34864] [101820 43777] [74001 43777]
+ )
+)
+Layer(2 "solder")
+(
+ Line[78740 59056 78740 68898 2500 2000 "clearline"]
+ Line[98425 39371 78740 59056 2500 2000 "clearline"]
+ Line[108268 59056 108268 68899 2500 2000 "clearline"]
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+ Line[49212 49214 39370 59056 2500 2000 "clearline"]
+ Line[68898 49214 49212 49214 2500 2000 "clearline"]
+ Line[59055 39371 59055 49214 2500 2000 "clearline"]
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+ Line[68898 49213 78740 39371 2500 2000 "clearline"]
+ Line[68898 49214 68898 49213 2500 2000 "clearline"]
+ Line[39370 88582 39371 88583 2500 2000 "clearline"]
+ Line[39370 39371 59055 39371 2500 2000 "clearline"]
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+ Line[98425 68899 68897 68899 2500 2000 "clearline"]
+ Line[108267 78741 98425 68899 2500 2000 "clearline"]
+ Line[108268 78741 108267 78741 2500 2000 "clearline"]
+ Line[108268 167324 108268 78741 2500 2000 "clearline"]
+ Line[88583 108269 88583 78741 2500 2000 "clearline"]
+ Line[59055 167324 49213 157482 2500 2000 "clearline"]
+ Line[88583 59056 98426 59056 2500 2000 "clearline"]
+ Line[88583 127953 88583 118111 1000 2000 "clearline"]
+ Line[59056 78742 59055 78741 2500 2000 "clearline"]
+ Line[59056 108269 59056 78742 2500 2000 "clearline"]
+ Line[29528 167324 39370 167324 2500 2000 "clearline"]
+ Line[78739 167323 78740 167324 1000 2000 "clearline"]
+ Line[49213 118111 49214 118111 600 1200 "clearline"]
+ Line[68898 137795 59056 127953 2500 2000 "clearline"]
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+ Line[68898 108269 68898 88583 2500 2000 "clearline"]
+ Line[78741 108269 78741 88583 2500 2000 "clearline"]
+ Line[39370 167324 39370 157482 2500 2000 "clearline"]
+ Line[88583 137796 88583 157481 2500 2000 "clearline"]
+ Line[78741 137795 78741 157481 2500 2000 "clearline"]
+ Line[68898 137795 68898 157481 2500 2000 "clearline"]
+ Line[49213 137796 49213 157481 2500 2000 "clearline"]
+ Line[39371 137796 39371 157481 2500 2000 "clearline"]
+ Line[98426 108269 98426 88583 2500 2000 "clearline"]
+ Line[78741 137795 88583 127953 2500 2000 "clearline"]
+ Line[39371 108269 49213 118111 2500 2000 "clearline"]
+ Line[39371 108269 39371 88583 2500 2000 "clearline"]
+ Line[88584 118111 98426 108269 2500 2000 "clearline"]
+ Line[88583 118111 88584 118111 2500 2000 "clearline"]
+ Line[59055 167323 68898 167323 2500 2000 "clearline"]
+ Line[78740 167324 88583 157481 2500 2000 "clearline"]
+ Line[68898 167323 78739 167323 1000 2000 "clearline"]
+ Line[141732 161417 141732 155512 1000 2000 "clearline"]
+ Arc[133858 161417 5905 5905 1000 2000 -90 -90 "clearline"]
+ Arc[149606 161418 5906 5906 1000 2000 -90 90 "clearline"]
+ Text[19176 128274 1 100 "500K/N" "clearline,auto"]
+ Text[67246 33668 0 100 "-" "clearline,auto"]
+ Text[28543 27561 0 100 "500K/N" "clearline,auto"]
+ Text[76771 27561 0 100 "500K/N" "clearline,auto"]
+ Text[57568 33972 0 100 "+" "clearline,auto"]
+ Text[70117 129711 0 100 "556" "clearline,auto"]
+ Text[37514 130772 0 100 "v0.1b" "clearline,auto"]
+ Text[134021 154801 0 100 "ATARI" "clearline,auto"]
+ Text[113780 61813 0 100 "-" "clearline,auto"]
+ Text[60141 119749 0 100 "HARVIE" "clearline,auto"]
+ Text[104357 35012 0 100 "out" "clearline,auto"]
+ Text[28629 183747 0 100 "BRMLAB ATARI PUNK CONSOLE" "clearline,auto"]
+ Polygon("clearpoly")
+ (
+ [19685 29529] [118110 29529] [118110 187009] [19685 187009]
+ )
+)
+Layer(3 "GND")
+(
+)
+Layer(4 "power")
+(
+)
+Layer(5 "signal1")
+(
+)
+Layer(6 "signal2")
+(
+)
+Layer(7 "signal3")
+(
+)
+Layer(8 "signal4")
+(
+)
+Layer(9 "silk")
+(
+)
+Layer(10 "silk")
+(
+)
+NetList()
+(
+ Net("GND" "(unknown)")
+ (
+ Connect("C?-2")
+ Connect("Q?-S")
+ Connect("U?-5")
+ Connect("V?-2")
+ )
+ Net("unnamed_net1" "(unknown)")
+ (
+ Connect("C?-1")
+ Connect("R?-1")
+ Connect("U?-1")
+ Connect("U?-9")
+ )
+ Net("unnamed_net2" "(unknown)")
+ (
+ Connect("R?-2")
+ Connect("U?-2")
+ )
+ Net("unnamed_net3" "(unknown)")
+ (
+ Connect("Q?-G")
+ Connect("U?-4")
+ )
+ Net("unnamed_net4" "(unknown)")
+ (
+ Connect("R?-2")
+ Connect("U?-11")
+ )
+ Net("unnamed_net5" "(unknown)")
+ (
+ Connect("C?-2")
+ Connect("U?-6")
+ )
+ Net("unnamed_net6" "(unknown)")
+ (
+ Connect("C?-1")
+ Connect("U?-7")
+ )
+ Net("unnamed_net7" "(unknown)")
+ (
+ Connect("Q?-D")
+ Connect("T?-3")
+ )
+ Net("unnamed_net8" "(unknown)")
+ (
+ Connect("T?-2")
+ Connect("U?-2")
+ )
+ Net("unnamed_net9" "(unknown)")
+ (
+ Connect("T?-4")
+ Connect("V?-1")
+ )
+ Net("unnamed_net10" "(unknown)")
+ (
+ Connect("T?-5")
+ Connect("U?-1")
+ )
+ Net("VDD" "(unknown)")
+ (
+ Connect("U?-14")
+ Connect("U?-16")
+ )
+ Net("VSS" "(unknown)")
+ (
+ Connect("U?-7")
+ Connect("U?-8")
+ )
+)
--- /dev/null
+v 20110115 2
+C 40000 40000 0 0 0 title-B.sym
+C 42500 47200 1 0 0 40106-1.sym
+{
+T 44200 47600 5 10 0 0 0 0 1
+device=40106
+T 44200 47800 5 10 0 0 0 0 1
+footprint=none
+T 42800 48100 5 10 1 1 0 0 1
+refdes=U?
+}
+C 45300 46300 1 0 0 4046-1.sym
+{
+T 45601 49850 5 10 0 0 0 0 1
+device=4046
+T 47000 49700 5 10 1 1 0 6 1
+refdes=U?
+T 45600 50050 5 10 0 0 0 0 1
+footprint=DIP16
+}
+C 41600 46900 1 270 0 capacitor-2.sym
+{
+T 42300 46700 5 10 0 0 270 0 1
+device=POLARIZED_CAPACITOR
+T 42100 46700 5 10 1 1 270 0 1
+refdes=C?
+T 42500 46700 5 10 0 0 270 0 1
+symversion=0.1
+}
+C 47300 47000 1 0 0 capacitor-2.sym
+{
+T 47500 47700 5 10 0 0 0 0 1
+device=POLARIZED_CAPACITOR
+T 47500 47500 5 10 1 1 0 0 1
+refdes=C?
+T 47500 47900 5 10 0 0 0 0 1
+symversion=0.1
+}
+C 43400 46800 1 0 0 pot-1.sym
+{
+T 44200 47700 5 10 0 0 0 0 1
+device=VARIABLE_RESISTOR
+T 44000 47200 5 10 1 1 0 0 1
+refdes=R?
+T 44200 48300 5 10 0 0 0 0 1
+footprint=none
+}
+C 41600 45700 1 0 0 ground.sym
+C 45100 46900 1 0 0 ground.sym
+C 49200 47300 1 0 0 ground.sym
+C 48400 47500 1 0 0 pot-bourns.sym
+{
+T 49200 48400 5 10 0 0 0 0 1
+device=VARIABLE_RESISTOR
+T 49000 47900 5 10 1 1 0 0 1
+refdes=R?
+}
+C 49500 48200 1 0 0 nmos-3.sym
+{
+T 50100 48700 5 10 0 0 0 0 1
+device=NMOS_TRANSISTOR
+T 50200 48800 5 10 1 1 0 0 1
+refdes=Q?
+}
+C 49800 47900 1 0 0 ground.sym
+C 51500 50300 1 180 0 transformer-3.sym
+{
+T 51500 48900 5 10 1 1 180 0 1
+refdes=T?
+T 51500 48700 5 10 0 0 180 0 1
+device=TRANSFORMER
+}
+C 52700 49600 1 90 0 beeper-1.sym
+{
+T 51800 49900 5 10 0 0 90 0 1
+device=BEEPER
+T 52000 49900 5 10 1 1 90 0 1
+refdes=U?
+T 51600 49900 5 10 0 0 90 0 1
+symversion=0.1
+}
+C 48500 49000 1 0 0 vdc-1.sym
+{
+T 49200 49650 5 10 1 1 0 0 1
+refdes=V?
+T 49200 49850 5 10 0 0 0 0 1
+device=VOLTAGE_SOURCE
+T 49200 50050 5 10 0 0 0 0 1
+footprint=none
+T 49200 49450 5 10 1 1 0 0 1
+value=DC 12V
+}
+C 48600 48700 1 0 0 ground.sym
+U 49300 47600 49400 47600 10 0
+N 41800 48300 45300 48300 4
+N 41800 46900 41800 48300 4
+N 41800 47700 42500 47700 4
+N 41800 46900 43400 46900 4
+N 48800 50200 50000 50200 4
+N 49500 48400 47300 48400 4
+N 47300 48100 48900 48100 4
+N 48200 47200 48200 47500 4
+N 48200 47500 47300 47500 4
+N 43900 47400 43900 47700 4
+N 43900 47700 43800 47700 4
+N 52400 50600 51500 50600 4
+N 51500 50600 51500 50200 4
+N 51500 49600 52400 49600 4
--- /dev/null
+555 soldering station
+
+http://www.falstad.com/circuit/#%24+1+5.0E-6+5.023272298708815+64+7.0+50%0Aw+304+144+272+144+0%0Aw+272+240+304+240+0%0Ag+272+304+272+320+0%0Aw+272+80+368+80+0%0AR+272+80+208+80+0+0+40.0+10.0+0.0+0.0+0.5%0AO+432+176+496+176+0%0A165+304+112+320+112+2+10.0%0Aw+368+80+432+80+0%0Ap+368+272+448+272+0%0Ag+448+272+496+272+0%0Ag+208+176+176+144+0%0Ap+208+176+272+208+0%0Aw+432+80+432+144+0%0Ag+272+144+272+160+0%0Aw+272+208+272+240+0%0A172+368+272+368+368+0+6+2.7+5.0+0.0+0.0+0.5+Voltage%0A172+272+240+160+240+0+6+0.4+5.0+0.0+0.0+0.5+Voltage%0Aw+304+144+304+160+0%0Aw+304+160+304+208+0%0Ao+5+32+0+42+10.0+9.765625E-5+0+-1%0Ao+8+64+0+34+5.0+9.765625E-5+1+-1%0Ao+11+64+0+34+2.5+9.765625E-5+2+-1%0A
+
+http://www.falstad.com/circuit/#%24+1+5.0E-6+5.023272298708815+64+7.0+50%0Aw+512+240+480+240+0%0Aw+480+336+512+336+0%0Aw+480+176+576+176+0%0AR+480+176+416+176+0+0+40.0+10.0+0.0+0.0+0.5%0AO+640+272+704+272+0%0A165+512+208+528+208+2+10.0%0Aw+576+176+640+176+0%0Ap+576+368+656+368+0%0Ag+656+368+704+368+0%0Ag+416+272+384+240+0%0Ap+416+272+480+304+0%0Aw+640+176+640+240+0%0Ag+480+240+480+256+0%0Aw+480+304+480+336+0%0Aw+512+240+512+256+0%0Aw+512+256+512+304+0%0Aw+480+176+480+112+0%0Aw+480+112+320+112+0%0Aw+320+352+320+416+0%0Ag+576+416+576+432+0%0Ar+464+416+576+416+0+500000.0%0Ar+576+464+464+464+0+500000.0%0Ag+576+464+576+480+0%0Aw+464+464+448+464+0%0A174+448+464+320+432+0+500000.0+0.5+Thermistor%0A174+464+416+400+400+0+500000.0+0.5+Temperature+set%0Aw+320+416+384+432+0%0Aw+464+464+496+368+0%0Aw+496+368+576+368+0%0Aw+464+416+480+336+0%0Aw+432+400+320+352+0%0Aw+320+352+320+112+0%0Ao+4+32+0+42+10.0+9.765625E-5+0+-1%0Ao+7+64+0+34+10.0+9.765625E-5+1+-1%0Ao+10+64+0+34+20.0+9.765625E-5+2+-1%0A
+
+$ 1 5.0E-6 5.023272298708815 64 7.0 50
+w 592 192 560 192 0
+w 560 288 592 288 0
+w 560 128 656 128 0
+R 560 128 496 128 0 0 40.0 10.0 0.0 0.0 0.5
+O 720 224 784 224 0
+165 592 160 608 160 2 10.0
+w 656 128 720 128 0
+p 656 320 736 320 0
+g 736 320 784 320 0
+g 496 224 464 192 0
+p 496 224 560 256 0
+w 720 128 720 192 0
+g 560 192 560 208 0
+w 560 256 560 288 0
+w 592 192 592 208 0
+w 592 208 592 256 0
+w 560 128 560 64 0
+w 560 64 400 64 0
+w 400 304 400 368 0
+g 512 464 512 480 0
+174 464 416 400 400 0 500000.0 0.47030000000000005 Temperature set
+w 576 320 656 320 0
+w 400 304 400 64 0
+r 480 320 480 368 0 500000.0
+w 400 368 400 384 0
+g 480 368 480 384 0
+w 480 320 560 288 0
+w 576 320 512 416 0
+r 512 416 512 464 0 500000.0
+w 464 416 512 416 0
+w 432 400 432 384 0
+w 432 384 400 384 0
+174 416 320 480 320 0 500000.0 0.48020000000000007 Thermistor
+w 448 304 448 288 0
+w 400 304 400 288 0
+w 400 288 448 288 0
+o 4 32 0 42 10.0 9.765625E-5 0 -1
+o 7 64 0 34 10.0 9.765625E-5 1 -1
+o 10 64 0 34 20.0 9.765625E-5 2 -1
--- /dev/null
+# release: pcb 20100929
+# date: Mon Jun 20 00:39:26 2011
+# user: harvie ()
+# host: insomnia
+
+# To read pcb files, the pcb version (or the git source date) must be >= the file version
+FileVersion[20100606]
+
+PCB["" 600000 500000]
+
+Grid[3937.008057 0 0 1]
+Cursor[0 0 0.000000]
+PolyArea[200000000.000000]
+Thermal[0.500000]
+DRC[1000 1000 1000 1000 1500 1000]
+Flags("nameonpcb,clearnew,snappin")
+Groups("1,c:2,s:3:4:5:6:7:8")
+Styles["Signal,1000,3600,2000,1000:Power,2500,6000,3500,1000:Fat,4000,6000,3500,1000:Skinny,600,2402,1181,600"]
+
+Symbol(' ' 18)
+(
+)
+Symbol('!' 12)
+(
+ SymbolLine(0 45 0 50 8)
+ SymbolLine(0 10 0 35 8)
+)
+Symbol('"' 12)
+(
+ SymbolLine(0 10 0 20 8)
+ SymbolLine(10 10 10 20 8)
+)
+Symbol('#' 12)
+(
+ SymbolLine(0 35 20 35 8)
+ SymbolLine(0 25 20 25 8)
+ SymbolLine(15 20 15 40 8)
+ SymbolLine(5 20 5 40 8)
+)
+Symbol('$' 12)
+(
+ SymbolLine(15 15 20 20 8)
+ SymbolLine(5 15 15 15 8)
+ SymbolLine(0 20 5 15 8)
+ SymbolLine(0 20 0 25 8)
+ SymbolLine(0 25 5 30 8)
+ SymbolLine(5 30 15 30 8)
+ SymbolLine(15 30 20 35 8)
+ SymbolLine(20 35 20 40 8)
+ SymbolLine(15 45 20 40 8)
+ SymbolLine(5 45 15 45 8)
+ SymbolLine(0 40 5 45 8)
+ SymbolLine(10 10 10 50 8)
+)
+Symbol('%' 12)
+(
+ SymbolLine(0 15 0 20 8)
+ SymbolLine(0 15 5 10 8)
+ SymbolLine(5 10 10 10 8)
+ SymbolLine(10 10 15 15 8)
+ SymbolLine(15 15 15 20 8)
+ SymbolLine(10 25 15 20 8)
+ SymbolLine(5 25 10 25 8)
+ SymbolLine(0 20 5 25 8)
+ SymbolLine(0 50 40 10 8)
+ SymbolLine(35 50 40 45 8)
+ SymbolLine(40 40 40 45 8)
+ SymbolLine(35 35 40 40 8)
+ SymbolLine(30 35 35 35 8)
+ SymbolLine(25 40 30 35 8)
+ SymbolLine(25 40 25 45 8)
+ SymbolLine(25 45 30 50 8)
+ SymbolLine(30 50 35 50 8)
+)
+Symbol('&' 12)
+(
+ SymbolLine(0 45 5 50 8)
+ SymbolLine(0 15 0 25 8)
+ SymbolLine(0 15 5 10 8)
+ SymbolLine(0 35 15 20 8)
+ SymbolLine(5 50 10 50 8)
+ SymbolLine(10 50 20 40 8)
+ SymbolLine(0 25 25 50 8)
+ SymbolLine(5 10 10 10 8)
+ SymbolLine(10 10 15 15 8)
+ SymbolLine(15 15 15 20 8)
+ SymbolLine(0 35 0 45 8)
+)
+Symbol(''' 12)
+(
+ SymbolLine(0 20 10 10 8)
+)
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+Via[9843 137795 6000 2000 0 3500 "" "thermal(0X)"]
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+Via[196851 137795 6000 2000 0 3500 "" "thermal(0X)"]
+Via[11811 66929 3600 2000 0 2000 "" ""]
+Via[11811 82677 3600 2000 0 2000 "" ""]
+Via[23622 66929 3600 2000 0 2000 "" ""]
+Via[23622 82677 3600 2000 0 2000 "" ""]
+Via[35433 66929 3600 2000 0 2000 "" ""]
+Via[35433 82677 3600 2000 0 2000 "" ""]
+Via[31496 82677 3600 2000 0 2000 "" ""]
+Via[43307 82677 3600 2000 0 2000 "" ""]
+Via[43307 66929 3600 2000 0 2000 "" ""]
+Via[47244 66929 3600 2000 0 2000 "" ""]
+Via[55118 82677 3600 2000 0 2000 "" ""]
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+Via[66929 82677 3600 2000 0 2000 "" ""]
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+Via[27559 66929 3600 2000 0 2000 "" ""]
+Via[15748 66929 3600 2000 0 2000 "" ""]
+Via[15748 82677 3600 2000 0 2000 "" ""]
+Layer(1 "component")
+(
+ Line[19685 9843 196851 9843 2500 2000 "clearline"]
+ Line[9843 19685 9843 59055 2500 2000 "clearline"]
+ Line[9843 88583 9843 127953 2500 2000 "clearline"]
+ Line[9843 19685 19685 9843 600 1200 "clearline"]
+ Line[19685 19685 19685 59055 2500 2000 "clearline"]
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+ Line[29528 19685 29528 59055 2500 2000 "clearline"]
+ Line[29528 88583 29528 127953 2500 2000 "clearline"]
+ Line[39370 19685 39370 59055 2500 2000 "clearline"]
+ Line[39370 88583 39370 127953 2500 2000 "clearline"]
+ Line[49213 19685 49213 59055 2500 2000 "clearline"]
+ Line[49213 88583 49213 127953 2500 2000 "clearline"]
+ Line[59055 19685 59055 59055 2500 2000 "clearline"]
+ Line[59055 88583 59055 127953 2500 2000 "clearline"]
+ Line[68898 19685 68898 59055 2500 2000 "clearline"]
+ Line[68898 88583 68898 127953 2500 2000 "clearline"]
+ Line[78740 19685 78740 59055 2500 2000 "clearline"]
+ Line[78740 88583 78740 127953 2500 2000 "clearline"]
+ Line[88583 19685 88583 59055 2500 2000 "clearline"]
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+ Line[98425 19685 98425 59055 2500 2000 "clearline"]
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+ Line[108268 19685 108268 59055 2500 2000 "clearline"]
+ Line[108268 88583 108268 127953 2500 2000 "clearline"]
+ Line[118110 19685 118110 59055 2500 2000 "clearline"]
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+ Line[127953 19685 127953 59055 2500 2000 "clearline"]
+ Line[127953 88583 127953 127953 2500 2000 "clearline"]
+ Line[137795 19685 137795 59055 2500 2000 "clearline"]
+ Line[137795 88583 137795 127953 2500 2000 "clearline"]
+ Line[147638 19685 147638 59055 2500 2000 "clearline"]
+ Line[147638 88583 147638 127953 2500 2000 "clearline"]
+ Line[157480 19685 157480 59055 2500 2000 "clearline"]
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+ Line[167323 19685 167323 59055 2500 2000 "clearline"]
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+ Line[177165 19685 177165 59055 2500 2000 "clearline"]
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+ Line[187008 19685 187008 59055 2500 2000 "clearline"]
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+ Line[196851 19685 196851 59055 2500 2000 "clearline"]
+ Line[196851 88583 196851 127953 2500 2000 "clearline"]
+ Line[9843 137795 196851 137795 2500 2000 "clearline"]
+ Line[11811 74803 15748 74803 1000 2000 "clearline"]
+ Line[70866 74803 74803 74803 1000 2000 "clearline"]
+ Line[74803 82677 70866 82677 1000 2000 "clearline"]
+ Line[78740 78740 74803 82677 1000 2000 "clearline"]
+ Line[74803 74803 78740 78740 1000 2000 "clearline"]
+ Line[78740 70866 74803 74803 1000 2000 "clearline"]
+ Line[74803 66929 78740 70866 1000 2000 "clearline"]
+ Line[70866 66929 74803 66929 1000 2000 "clearline"]
+ Line[70866 82677 70866 66929 1000 2000 "clearline"]
+ Line[59055 74803 66929 74803 1000 2000 "clearline"]
+ Line[66929 70866 66929 82677 1000 2000 "clearline"]
+ Line[62992 66929 66929 70866 1000 2000 "clearline"]
+ Line[59055 70866 62992 66929 1000 2000 "clearline"]
+ Line[59055 82677 59055 70866 1000 2000 "clearline"]
+ Line[51181 82677 55118 82677 1000 2000 "clearline"]
+ Line[47244 78740 51181 82677 1000 2000 "clearline"]
+ Line[47244 66929 47244 78740 1000 2000 "clearline"]
+ Line[43307 66929 43307 82677 1000 2000 "clearline"]
+ Line[43307 70866 43307 66929 1000 2000 "clearline"]
+ Line[39370 74803 43307 70866 1000 2000 "clearline"]
+ Line[35433 70866 39370 74803 1000 2000 "clearline"]
+ Line[35433 66929 35433 70866 1000 2000 "clearline"]
+ Line[35433 66929 35433 82677 1000 2000 "clearline"]
+ Line[31496 78740 31496 82677 1000 2000 "clearline"]
+ Line[27559 74803 31496 78740 1000 2000 "clearline"]
+ Line[27559 74803 23622 74803 1000 2000 "clearline"]
+ Line[31496 70866 27559 74803 1000 2000 "clearline"]
+ Line[27559 66929 31496 70866 1000 2000 "clearline"]
+ Line[23622 66929 27559 66929 1000 2000 "clearline"]
+ Line[23622 66929 23622 82677 1000 2000 "clearline"]
+ Line[15748 66929 11811 66929 1000 2000 "clearline"]
+ Line[19685 70866 15748 66929 1000 2000 "clearline"]
+ Line[15748 74803 19685 70866 1000 2000 "clearline"]
+ Line[19685 78740 15748 74803 1000 2000 "clearline"]
+ Line[15748 82677 19685 78740 1000 2000 "clearline"]
+ Line[11811 82677 15748 82677 1000 2000 "clearline"]
+ Line[11811 66929 11811 82677 1000 2000 "clearline"]
+ Text[8470 1400 0 100 "-" "clearline"]
+ Text[18419 1400 0 100 "+" "clearline"]
+ Polygon("clearpoly")
+ (
+ [206693 147638] [0 147638] [0 0] [206693 0]
+ )
+)
+Layer(2 "solder")
+(
+)
+Layer(3 "GND")
+(
+)
+Layer(4 "power")
+(
+)
+Layer(5 "signal1")
+(
+)
+Layer(6 "signal2")
+(
+)
+Layer(7 "signal3")
+(
+)
+Layer(8 "signal4")
+(
+)
+Layer(9 "silk")
+(
+)
+Layer(10 "silk")
+(
+)
--- /dev/null
+svorky:
+1x zem
+2x zaporna
+3x kladna
+(1x standby - USB)
+
+1x vypinac
--- /dev/null
+_*
+*~
+*.stl
--- /dev/null
+/*
+ * TODO
+ ** make more parametric
+ ** add parameter to specify number of wires/pins
+ */
+
+$fn=10; //Minimum nuber of circle segments
+
+module conn_male(size=23, thickness=1.5, full=false) {
+ difference() {
+ union() {
+ translate([0,size*0.3,0]) cube([size-(thickness*2),(size-(thickness*2))*2,size-(thickness*2)], center=true);
+ translate([size/3,(size/3)-thickness]) rotate([0,0,145]) cube([size*0.2,size/4,size-(thickness*2)], center=true);
+ }
+ if(!full) {
+ translate([0,size/2,0]) cube([size-(thickness*4),size*1.5,size+1], center=true);
+ rotate([0,90,0])
+ for(i = [(size/3)-thickness,-(size/3)+thickness])
+ translate([i,0,0])
+ rotate([90,0,0])
+ cylinder(size*2, size/10, size/10);
+ }
+ }
+}
+
+module conn_female(size=23, thickness=1.5) {
+ difference() {
+ cube(size, center=true);
+ conn_male(size, thickness=thickness, full=true);
+ for(i = [size/4,-size/4])
+ translate([i,0,0])
+ rotate([90,0,0]) cylinder(size*2, size/10, size/10);
+ }
+}
+
+module connector(size=10, thickness=1.5, gap=0.6, design=false) {
+ if(!design) {
+ //Print
+ translate([0,size*1.5,-(thickness+gap/2)]) conn_male(size-gap,thickness);
+ conn_female(size,thickness);
+ } else {
+ //Design
+ conn_male(size-gap,thickness);
+ % conn_female(size,thickness);
+ }
+}
+
+//connector(design=true);
+connector();
\ No newline at end of file
--- /dev/null
+module pagoda(scale=1, height=1, ratio=2, center=true) {
+ scale([scale,scale])
+ linear_extrude(height=height, center=center)
+ polygon(points=[[-1,1],[1,1],[1*ratio,-1],[-1*ratio,-1]], paths=[[0,1,2,3]]);
+}
+
+module female(thickness=0.3) {
+ difference() {
+ %cube([4,2+thickness,1+(2*thickness)], center=true);
+ translate([0,thickness,0]) pagoda(ratio=1.5);
+ }
+}
+
+module male() {
+ difference() {
+ pagoda(ratio=2, scale=0.9);
+ //translate([0,-0.7]) pagoda(ratio=2);
+ translate([0,-0.21]) pagoda(ratio=2, scale=0.7, height=1.1);
+ }
+}
+
+module connector(design=false) {
+ scale(4) if(!design) {
+ //Print
+ translate([0,3,0-1.15+0.5]) male();
+ rotate([90]) female();
+ } else {
+ //Design
+ male();
+ % female();
+ }
+}
+
+//connector(design=true);
+connector();
--- /dev/null
+/*
+ * TODO
+ ** make more parametric
+ ** add parameter to specify number of wires/pins
+ */
+
+$fn=10; //Minimum nuber of circle segments
+
+module conn_male(size=23, thickness=1.5, full=false) {
+ difference() {
+ union() {
+ translate([0,size*0.3,0]) cube([size-(thickness*2),(size-(thickness*2))*2,size-(thickness*2)], center=true);
+ translate([size/3,(size/3)-thickness]) rotate([0,0,145]) cube([size*0.2,size/4,size-(thickness*2)], center=true);
+ }
+ if(!full) {
+ translate([0,size/2,0]) cube([size-(thickness*4),size*1.5,size+1], center=true);
+ rotate([0,90,0])
+ for(i = [(size/3)-thickness,-(size/3)+thickness])
+ translate([i,0,0])
+ rotate([90,0,0])
+ cylinder(size*2, size/10, size/10);
+ }
+ }
+}
+
+module conn_female(size=23, thickness=1.5) {
+ difference() {
+ cube(size, center=true);
+ conn_male(size, thickness=thickness, full=true);
+ for(i = [size/4,-size/4])
+ translate([i,0,0])
+ rotate([90,0,0]) cylinder(size*2, size/10, size/10);
+ }
+}
+
+module connector(size=10, thickness=1.5, gap=0.6, design=false) {
+ if(!design) {
+ //Print
+ translate([0,size*1.5,-(thickness+gap/2)]) conn_male(size-gap,thickness);
+ conn_female(size,thickness);
+ } else {
+ //Design
+ conn_male(size-gap,thickness);
+ % conn_female(size,thickness);
+ }
+}
+
+//connector(design=true);
+connector();
\ No newline at end of file
GIT.Harvie.CZ / mirrors / Designs.git / commitdiff
