From b8ad78c0ace23e51b0c41cb213ab9301a854cf30 Mon Sep 17 00:00:00 2001
From: Harvie <tomas@mudrunka.cz>
Date: Fri, 26 Aug 2011 06:24:14 +0200
Subject: [PATCH] Added designs made before creating this repository

---
 electronics/.gitignore          |    8 +
 electronics/1bit-adc.png        |  Bin 0 -> 11316 bytes
 electronics/1bit-adc.sch        |   69 ++
 electronics/README.md           |    7 +
 electronics/apc-0.1b.png        |  Bin 0 -> 15612 bytes
 electronics/apc.pcb             | 1077 ++++++++++++++++++++++++++++
 electronics/apc.png             |  Bin 0 -> 9069 bytes
 electronics/devastator.sch      |  108 +++
 electronics/falstad.txt         |   46 ++
 electronics/stripboard.pcb      | 1177 +++++++++++++++++++++++++++++++
 electronics/zdroj-soucastky.txt |    7 +
 openscad/.gitignore             |    3 +
 openscad/connector.scad         |   49 ++
 openscad/repjack-test.scad      |   35 +
 openscad/repjack.scad           |   49 ++
 15 files changed, 2635 insertions(+)
 create mode 100644 electronics/.gitignore
 create mode 100644 electronics/1bit-adc.png
 create mode 100644 electronics/1bit-adc.sch
 create mode 100644 electronics/README.md
 create mode 100644 electronics/apc-0.1b.png
 create mode 100644 electronics/apc.pcb
 create mode 100644 electronics/apc.png
 create mode 100644 electronics/devastator.sch
 create mode 100644 electronics/falstad.txt
 create mode 100644 electronics/stripboard.pcb
 create mode 100644 electronics/zdroj-soucastky.txt
 create mode 100644 openscad/.gitignore
 create mode 100644 openscad/connector.scad
 create mode 100644 openscad/repjack-test.scad
 create mode 100644 openscad/repjack.scad

diff --git a/electronics/.gitignore b/electronics/.gitignore
new file mode 100644
index 0000000..ff336b6
--- /dev/null
+++ b/electronics/.gitignore
@@ -0,0 +1,8 @@
+_*
+*.cmd
+*.net
+*.backup
+*.ps
+*.eps
+*~
+*-
diff --git a/electronics/1bit-adc.png b/electronics/1bit-adc.png
new file mode 100644
index 0000000000000000000000000000000000000000..81b2c5c0d3388c318b9d0e7abe11c0da89dc6954
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diff --git a/electronics/1bit-adc.sch b/electronics/1bit-adc.sch
new file mode 100644
index 0000000..ab2124e
--- /dev/null
+++ b/electronics/1bit-adc.sch
@@ -0,0 +1,69 @@
+v 20110115 2
+C 40000 40000 0 0 0 title-B.sym
+C 42200 47500 1 0 0 lm358-1.sym
+{
+T 42875 48100 5 10 0 0 0 0 1
+device=LM358
+T 42900 48850 5 10 0 0 0 0 1
+footprint=DIP8
+T 42400 48400 5 10 1 1 0 0 1
+refdes=(or LM386)
+}
+C 40700 47800 1 0 0 pwrjack-1.sym
+{
+T 40800 48300 5 10 0 0 0 0 1
+device=PWRJACK
+T 40700 48300 5 10 1 1 0 0 1
+refdes=AUDIO IN
+}
+C 44500 47400 1 0 0 4066-1.sym
+{
+T 44800 49950 5 10 0 0 0 0 1
+device=4066
+T 46300 49800 5 10 1 1 0 6 1
+refdes=U?
+T 44800 50150 5 10 0 0 0 0 1
+footprint=DIP14
+}
+C 42000 47200 1 0 0 ground.sym
+C 41600 47600 1 0 0 ground.sym
+N 41600 47900 41800 47900 4
+N 41600 48100 42200 48100 4
+C 48100 49600 1 180 0 pwrjack-1.sym
+{
+T 48000 49100 5 10 0 0 180 0 1
+device=PWRJACK
+T 48100 49100 5 10 1 1 180 0 1
+refdes=AUDIO OUT
+}
+N 47200 49500 46600 49500 4
+C 46700 49000 1 0 0 ground.sym
+N 46900 49300 47200 49300 4
+C 43400 47700 1 0 0 capacitor-1.sym
+{
+T 43600 48400 5 10 0 0 0 0 1
+device=CAPACITOR
+T 43600 48200 5 10 1 1 0 0 1
+refdes=C?
+T 43600 48600 5 10 0 0 0 0 1
+symversion=0.1
+}
+C 44400 47000 1 90 0 resistor-2.sym
+{
+T 44050 47400 5 10 0 0 90 0 1
+device=RESISTOR
+T 44100 47200 5 10 1 1 90 0 1
+refdes=R?
+}
+C 44100 46700 1 0 0 ground.sym
+N 44300 47900 44500 47900 4
+C 44500 49700 1 180 0 voltage-3.sym
+{
+T 44300 49000 5 8 0 0 180 0 1
+device=VOLTAGE_SOURCE
+T 44200 49200 5 10 1 1 180 0 1
+refdes=V?
+}
+C 43400 49200 1 0 0 ground.sym
+N 43200 47900 43400 47900 4
+N 42200 47500 42200 47700 4
diff --git a/electronics/README.md b/electronics/README.md
new file mode 100644
index 0000000..eeaef31
--- /dev/null
+++ b/electronics/README.md
@@ -0,0 +1,7 @@
+# Harvie's electroprojects
+Some schematics, PCB designs and other electronics related stuff
+
+http://blog.harvie.cz/
+
+### Usefull Software
+  * http://www.gpleda.org/
diff --git a/electronics/apc-0.1b.png b/electronics/apc-0.1b.png
new file mode 100644
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diff --git a/electronics/apc.pcb b/electronics/apc.pcb
new file mode 100644
index 0000000..eba67bb
--- /dev/null
+++ b/electronics/apc.pcb
@@ -0,0 +1,1077 @@
+# release: pcb 20100929
+# date:    Mon Jun 20 04:40:22 2011
+# user:    harvie ()
+# host:    insomnia
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+	(
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+	Net("unnamed_net6" "(unknown)")
+	(
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+	(
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+	Net("unnamed_net10" "(unknown)")
+	(
+		Connect("T?-5")
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+	Net("VDD" "(unknown)")
+	(
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+	Net("VSS" "(unknown)")
+	(
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diff --git a/electronics/devastator.sch b/electronics/devastator.sch
new file mode 100644
index 0000000..143df0c
--- /dev/null
+++ b/electronics/devastator.sch
@@ -0,0 +1,108 @@
+v 20110115 2
+C 40000 40000 0 0 0 title-B.sym
+C 42500 47200 1 0 0 40106-1.sym
+{
+T 44200 47600 5 10 0 0 0 0 1
+device=40106
+T 44200 47800 5 10 0 0 0 0 1
+footprint=none
+T 42800 48100 5 10 1 1 0 0 1
+refdes=U?
+}
+C 45300 46300 1 0 0 4046-1.sym
+{
+T 45601 49850 5 10 0 0 0 0 1
+device=4046
+T 47000 49700 5 10 1 1 0 6 1
+refdes=U?
+T 45600 50050 5 10 0 0 0 0 1
+footprint=DIP16
+}
+C 41600 46900 1 270 0 capacitor-2.sym
+{
+T 42300 46700 5 10 0 0 270 0 1
+device=POLARIZED_CAPACITOR
+T 42100 46700 5 10 1 1 270 0 1
+refdes=C?
+T 42500 46700 5 10 0 0 270 0 1
+symversion=0.1
+}
+C 47300 47000 1 0 0 capacitor-2.sym
+{
+T 47500 47700 5 10 0 0 0 0 1
+device=POLARIZED_CAPACITOR
+T 47500 47500 5 10 1 1 0 0 1
+refdes=C?
+T 47500 47900 5 10 0 0 0 0 1
+symversion=0.1
+}
+C 43400 46800 1 0 0 pot-1.sym
+{
+T 44200 47700 5 10 0 0 0 0 1
+device=VARIABLE_RESISTOR
+T 44000 47200 5 10 1 1 0 0 1
+refdes=R?
+T 44200 48300 5 10 0 0 0 0 1
+footprint=none
+}
+C 41600 45700 1 0 0 ground.sym
+C 45100 46900 1 0 0 ground.sym
+C 49200 47300 1 0 0 ground.sym
+C 48400 47500 1 0 0 pot-bourns.sym
+{
+T 49200 48400 5 10 0 0 0 0 1
+device=VARIABLE_RESISTOR
+T 49000 47900 5 10 1 1 0 0 1
+refdes=R?
+}
+C 49500 48200 1 0 0 nmos-3.sym
+{
+T 50100 48700 5 10 0 0 0 0 1
+device=NMOS_TRANSISTOR
+T 50200 48800 5 10 1 1 0 0 1
+refdes=Q?
+}
+C 49800 47900 1 0 0 ground.sym
+C 51500 50300 1 180 0 transformer-3.sym
+{
+T 51500 48900 5 10 1 1 180 0 1
+refdes=T?
+T 51500 48700 5 10 0 0 180 0 1
+device=TRANSFORMER
+}
+C 52700 49600 1 90 0 beeper-1.sym
+{
+T 51800 49900 5 10 0 0 90 0 1
+device=BEEPER
+T 52000 49900 5 10 1 1 90 0 1
+refdes=U?
+T 51600 49900 5 10 0 0 90 0 1
+symversion=0.1
+}
+C 48500 49000 1 0 0 vdc-1.sym
+{
+T 49200 49650 5 10 1 1 0 0 1
+refdes=V?
+T 49200 49850 5 10 0 0 0 0 1
+device=VOLTAGE_SOURCE
+T 49200 50050 5 10 0 0 0 0 1
+footprint=none
+T 49200 49450 5 10 1 1 0 0 1
+value=DC 12V
+}
+C 48600 48700 1 0 0 ground.sym
+U 49300 47600 49400 47600 10 0
+N 41800 48300 45300 48300 4
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+N 41800 47700 42500 47700 4
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+N 43900 47400 43900 47700 4
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diff --git a/electronics/falstad.txt b/electronics/falstad.txt
new file mode 100644
index 0000000..5072568
--- /dev/null
+++ b/electronics/falstad.txt
@@ -0,0 +1,46 @@
+555 soldering station
+
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diff --git a/electronics/stripboard.pcb b/electronics/stripboard.pcb
new file mode 100644
index 0000000..ec7415b
--- /dev/null
+++ b/electronics/stripboard.pcb
@@ -0,0 +1,1177 @@
+# release: pcb 20100929
+# date:    Mon Jun 20 00:39:26 2011
+# user:    harvie ()
+# host:    insomnia
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+# To read pcb files, the pcb version (or the git source date) must be >= the file version
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+	Line[35433 70866 39370 74803 1000 2000 "clearline"]
+	Line[35433 66929 35433 70866 1000 2000 "clearline"]
+	Line[35433 66929 35433 82677 1000 2000 "clearline"]
+	Line[31496 78740 31496 82677 1000 2000 "clearline"]
+	Line[27559 74803 31496 78740 1000 2000 "clearline"]
+	Line[27559 74803 23622 74803 1000 2000 "clearline"]
+	Line[31496 70866 27559 74803 1000 2000 "clearline"]
+	Line[27559 66929 31496 70866 1000 2000 "clearline"]
+	Line[23622 66929 27559 66929 1000 2000 "clearline"]
+	Line[23622 66929 23622 82677 1000 2000 "clearline"]
+	Line[15748 66929 11811 66929 1000 2000 "clearline"]
+	Line[19685 70866 15748 66929 1000 2000 "clearline"]
+	Line[15748 74803 19685 70866 1000 2000 "clearline"]
+	Line[19685 78740 15748 74803 1000 2000 "clearline"]
+	Line[15748 82677 19685 78740 1000 2000 "clearline"]
+	Line[11811 82677 15748 82677 1000 2000 "clearline"]
+	Line[11811 66929 11811 82677 1000 2000 "clearline"]
+	Text[8470 1400 0 100 "-" "clearline"]
+	Text[18419 1400 0 100 "+" "clearline"]
+	Polygon("clearpoly")
+	(
+		[206693 147638] [0 147638] [0 0] [206693 0] 
+	)
+)
+Layer(2 "solder")
+(
+)
+Layer(3 "GND")
+(
+)
+Layer(4 "power")
+(
+)
+Layer(5 "signal1")
+(
+)
+Layer(6 "signal2")
+(
+)
+Layer(7 "signal3")
+(
+)
+Layer(8 "signal4")
+(
+)
+Layer(9 "silk")
+(
+)
+Layer(10 "silk")
+(
+)
diff --git a/electronics/zdroj-soucastky.txt b/electronics/zdroj-soucastky.txt
new file mode 100644
index 0000000..8d6124d
--- /dev/null
+++ b/electronics/zdroj-soucastky.txt
@@ -0,0 +1,7 @@
+svorky:
+1x zem
+2x zaporna
+3x kladna
+(1x standby - USB)
+
+1x vypinac
diff --git a/openscad/.gitignore b/openscad/.gitignore
new file mode 100644
index 0000000..f06925c
--- /dev/null
+++ b/openscad/.gitignore
@@ -0,0 +1,3 @@
+_*
+*~
+*.stl
diff --git a/openscad/connector.scad b/openscad/connector.scad
new file mode 100644
index 0000000..d09ed2c
--- /dev/null
+++ b/openscad/connector.scad
@@ -0,0 +1,49 @@
+/*
+ * TODO
+ ** make more parametric
+ ** add parameter to specify number of wires/pins
+ */
+
+$fn=10; //Minimum nuber of circle segments
+
+module conn_male(size=23, thickness=1.5, full=false) {
+	difference() {
+		union() {
+			translate([0,size*0.3,0]) cube([size-(thickness*2),(size-(thickness*2))*2,size-(thickness*2)], center=true);
+			translate([size/3,(size/3)-thickness]) rotate([0,0,145]) cube([size*0.2,size/4,size-(thickness*2)], center=true);
+		}
+		if(!full) {
+			translate([0,size/2,0]) cube([size-(thickness*4),size*1.5,size+1], center=true);
+			rotate([0,90,0])
+			for(i = [(size/3)-thickness,-(size/3)+thickness])
+				translate([i,0,0]) 
+				rotate([90,0,0])
+				cylinder(size*2, size/10, size/10);
+		}
+	}
+}
+
+module conn_female(size=23, thickness=1.5) {
+	difference() {
+		cube(size, center=true);
+		conn_male(size, thickness=thickness, full=true);
+		for(i = [size/4,-size/4])
+			translate([i,0,0]) 
+			rotate([90,0,0]) cylinder(size*2, size/10, size/10);
+	}
+}
+
+module connector(size=10, thickness=1.5, gap=0.6, design=false) {
+	if(!design) {
+		//Print
+		translate([0,size*1.5,-(thickness+gap/2)]) conn_male(size-gap,thickness);
+		conn_female(size,thickness);
+	} else {
+		//Design
+		conn_male(size-gap,thickness);
+		% conn_female(size,thickness);
+	}
+}
+
+//connector(design=true);
+connector();
\ No newline at end of file
diff --git a/openscad/repjack-test.scad b/openscad/repjack-test.scad
new file mode 100644
index 0000000..7843b0d
--- /dev/null
+++ b/openscad/repjack-test.scad
@@ -0,0 +1,35 @@
+module pagoda(scale=1, height=1, ratio=2, center=true) {
+	scale([scale,scale])
+	linear_extrude(height=height, center=center)
+	polygon(points=[[-1,1],[1,1],[1*ratio,-1],[-1*ratio,-1]], paths=[[0,1,2,3]]);
+}
+
+module female(thickness=0.3) {
+	difference() {
+		%cube([4,2+thickness,1+(2*thickness)], center=true);
+		translate([0,thickness,0]) pagoda(ratio=1.5);
+	}
+}
+
+module male() {
+	difference() {
+		pagoda(ratio=2, scale=0.9);		
+		//translate([0,-0.7]) pagoda(ratio=2);
+		translate([0,-0.21]) pagoda(ratio=2, scale=0.7, height=1.1);
+	}
+}
+
+module connector(design=false) {
+	scale(4) if(!design) {
+		//Print
+		translate([0,3,0-1.15+0.5]) male();
+		rotate([90]) female();
+	} else {
+		//Design
+		male();
+		% female();
+	}
+}
+
+//connector(design=true);
+connector();
diff --git a/openscad/repjack.scad b/openscad/repjack.scad
new file mode 100644
index 0000000..d09ed2c
--- /dev/null
+++ b/openscad/repjack.scad
@@ -0,0 +1,49 @@
+/*
+ * TODO
+ ** make more parametric
+ ** add parameter to specify number of wires/pins
+ */
+
+$fn=10; //Minimum nuber of circle segments
+
+module conn_male(size=23, thickness=1.5, full=false) {
+	difference() {
+		union() {
+			translate([0,size*0.3,0]) cube([size-(thickness*2),(size-(thickness*2))*2,size-(thickness*2)], center=true);
+			translate([size/3,(size/3)-thickness]) rotate([0,0,145]) cube([size*0.2,size/4,size-(thickness*2)], center=true);
+		}
+		if(!full) {
+			translate([0,size/2,0]) cube([size-(thickness*4),size*1.5,size+1], center=true);
+			rotate([0,90,0])
+			for(i = [(size/3)-thickness,-(size/3)+thickness])
+				translate([i,0,0]) 
+				rotate([90,0,0])
+				cylinder(size*2, size/10, size/10);
+		}
+	}
+}
+
+module conn_female(size=23, thickness=1.5) {
+	difference() {
+		cube(size, center=true);
+		conn_male(size, thickness=thickness, full=true);
+		for(i = [size/4,-size/4])
+			translate([i,0,0]) 
+			rotate([90,0,0]) cylinder(size*2, size/10, size/10);
+	}
+}
+
+module connector(size=10, thickness=1.5, gap=0.6, design=false) {
+	if(!design) {
+		//Print
+		translate([0,size*1.5,-(thickness+gap/2)]) conn_male(size-gap,thickness);
+		conn_female(size,thickness);
+	} else {
+		//Design
+		conn_male(size-gap,thickness);
+		% conn_female(size,thickness);
+	}
+}
+
+//connector(design=true);
+connector();
\ No newline at end of file
-- 
2.30.2